RESEARCH



Modulation Scheme

High speed communication Link

The ever-increasing demand for bandwidth drives the incessant development of power-efficient high-speed communication systems. The skin and dielectric losses in high-speed wireline channel require an equalizer to compensate for the intersymbol interference (ISI).

Next Generation TRX Solution

Time-domain modulation splits time for carrying more information. The divided time expands data rate compared to NRZ for equivalentoperating frequency, so it enhance spectral efficiency. This leads reduction of insertion loss on channel that lower equalization complexity can be achieved.


All-rate CDR

Emergence of new communication
standards and the backward compatibility

The continuous-rate CDR has been proposed to achieve the backward compatibility. Ring VCO-based CDRs are not acceptable due to the high phase noise, and multiple LC VCO-based CDRs require a large chip area.

Conventional continuous-rate CDR

The continuous-rate CDR has been proposed to achieve the backward compatibility. Ring VCO-based CDRs are not acceptable due to the high phase noise, and multiple LC VCO -based CDRs require a large chip area.

All-rate CDR with a single LC VCO

All-rate CDR with a single LC VCO supports the backward compatibility and overcomes drawbacks of the conventional continuous-rate CDR. All-rate clock ivider facilitates all-rate CDR operation with a single LC VCO. It achieves a low phase noise clock with all-rate clock frequency.

Memory Interface

Demands of Server Memory

Nowadays, as DATA for server to deal with become much larger, the server memory requires more capacities, higher speed, smaller area and lower power consumption. So far, it has been semiconductor process-downscaling that makes such specifications possible on memory. However, this approach is not suitable, lately, so that people may try another ways to satisfy more demands now and in future.

Low power High performance
Next Generation Memory Interface

Recently, there are poor signal and power integrities (SI & PI) on memory interface performance owing to the limit of trade-off: high data rate and large capacity, but small area. We are developing next generation memory interface chips which enables DIMM with more capacities, higher bandwidth due to improved SI & PI. Thus, it ill be able to be used in server computer system at the same conventional mainboard channel environment.

Programmable CDR

Programmable CDR

As IC fabrication minimum dimensions are getting smaller, Multi-Project Wafer (MPW) cost is significantly increased. In addition, simulation time for verifying new algorithm is big portion of total system development time. We designed programmable CDR to dramatically reduce the time and economic cost of a system development.

System Architecture

There is CDR loop including analog ASIC unit and digital FPGA unit. For using digital loop filter (DLF), the oscillator and the phase-rotators are digitally controlled. This system has many building blocks which can be turned on and off. So, we can use this system as another system¡?s building block by using appropriate combination.

EDC




EDC


EDC (PON)

Dispersion is a problem that must be considered when transmitting signals over optical links because it introduces inter-symbol interference. By compensating for dispersion effects, our EDC extends the reach and allows low-cost DML to be used in many applications which otherwise require more expensive EML. Our technology can be combined with other circuitry in both 10- and 25-Gb/s transceiver IC designs without significant power and complexity overhead. Thus, the increased transmission distance or the significant savings in laser cost can be achieved at only modest increases in IC cost.


Silicon Photonics

Si-Photonics

Si-photonics is the silicon based optical communication solution for near future. Optical technology is very robust to electrical one in terms of loss, noise, and dispersion. However, high speed lasers are too expensive to use relatively short length comm. Modulator photonic IC which is made of silicon can replace the laser to much cheaper laser.

Next Generation TRX Solution

Si-photonics based transceiver is consist of laser, photo detector, modulator, filter, and fiber coupler. Modulators shift some phase of the light from laser. Phase-shifted light interferences with the light from other optical path on filter. This filtered light information is guided from chip to fiber. Transmitted optical signal is converted to electrical one on photo-detector.

Overall Publication List

Sejun Jeon, WooHyun Kwon, Jong-Hyeok Yoon, Taehun Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae, “A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links”, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), April 2020.

Kyeongha Kwon, Jong-Hyeok Yoon, Younho Jeon, Hanho Choi, Sejun Jeon, Hyeon-Min Bae, “An Electronic Dispersion Compensation Transceiver for 10-Gb/s and 28-Gb/s Directly Modulated Lasers-Based Optical Link”, IEEE Journal of Solid-State Circuits (JSSC), no. 1, vol. 54, Jan. 2019.

Jong-Hyeok Yoon, Kyeongha Kwon, Hyeon-Min Bae, “A 3.125-to-28.125 Gb/s Multi-Standard Transceiver with a Fully Channel-independent Operation in 40nm CMOS”, IEEE Custom Integrated Circuits Conference (CICC), April 2018.

Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae, “A 28Gb/s transceiver with chirp-managed EDC for DML systems”, IEEE International Solid State Circuit Conference (ISSCC), Feb. 2018.

Sejun Jeon, WooHyun Kwon, Taehun Yoon, Jong-Hyeok Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae, “A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS”, IEEE International Solid State Circuit Conference (ISSCC), Feb. 2018.

Taehun Yoon, Joon-Yeong Lee, Kwangseok Han, Jeongsup Lee, Taeho Kim, Hyosup Won, Jinho Park, Hyeon-Min Bae, “A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links”, IEEE Journal of Solid State Circuits, no. 3, pp. 688-703, March 2017.

Jong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae, “A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single LC VCO in 90 nm CMOS”, IEEE Journal of Solid State Circuits (ISSCC), no. 3, pp. 856-866, March 2017.

Hyosup Won, Joon-Yeong Lee, Taehun Yoon, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae, “A 28-Gb/s Receiver with Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-tracking Eye-opening Monitor”, IEEE Transactions on Circuits and Systems I : Regular Papers, Dec. 2016.

Joon-Yeong Lee, Kwangseok Han, Taehun Yoon, Taeho Kim, Sang-Eun Lee, Jeong-Sup Lee, Jinho Park, Hyeon-Min Bae, “A Power-and-Area Efficient 10 x 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation”, IEEE Journal of Solid-State Circuits, no. 10, pp. 2475-2484, Oct. 2016.

Soon-Won Kwon, Joon-Yeong Lee, Jinhee Lee, Kwangseok Han, Taeho Kim, Sang-Eun Lee, Jeong-Sup Lee, Taehun Yoon, Hyosup Won, Jinho Park, Hyeon-Min Bae, “An automatic loop gain control algorithm for Bang-Bang CDRs”, IEEE Transactions on Circuits and Systems I : Regular Papers, no. 12, pp. 2817-2828, Dec. 2015.

Joon-Yeong Lee, Jaehyeok Yang, Jong-Hyeok Yoon, Soon-Won Kwon, Hyosup Won, Jinho Han, Hyeon-Min Bae, “A 4 x 10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no. 6, pp. 2310-2320, Sept. 2015.

Jong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae, “A DC-to-12.5Gb/s 4.88mW/Gb/s All-rate CDR with a single LC VCO in 90nm CMOS”, IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Sept. 2015.

Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sang-Eun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae, “A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation”, IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Sept. 2015.

Hyosup Won, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae, “An On-chip Stochastic Sigma-tracking Eye-opening Monitor for BER-optimal Adaptive Equalization”, IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Sept. 2015.

Taehun Yoon, Joon-Yeong Lee, Kwangseok Han, Jeongsup Lee, Taeho Kim, Hyosup Won, Jinho Park, Hyeon-Min Bae, “A 100-GbE Reverse Gearbox IC in 40nm CMOS for Supporting Legacy 10- and 40-GbE Standard”, IEEE Symposium on VLSI Circuits, pp. C212-C213, June 2015.

Hyosup Won, Taehun Yoon, Jinho Han, Joon-Yeong Lee, Jong-Hyeok Yoon, Hyeon-Min Bae, “A 0.87-W Transceiver IC for 100-Gigabit Ethernet in 40-nm CMOS”, IEEE Journal of Solid-State Circuits, no. 2, pp. 399-413, Feb. 2015.

Kyeongha Kwon, Jong-Hyeok Yoon, Hyeon-Min Bae, “A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers”, IEEE Journal of Solid-State Circuits, no. 2, pp. 503-514, Feb. 2015.

Joon-Yeong Lee, Jong-Hyeok Yoon, Hyeon-Min Bae, “A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links”, IEEE Transactions on Circuits and Systems I: Regular Papers, no. 8, pp. 2466-2472, Aug. 2014.

Sejun Jeon, Hyosup Won, Hyeon-Min Bae, “BER-Aware ADC-Based 2 X 1 MIMO Blind Receiver for High Speed Broadband Communication Links”, IEEE Transactions on Circuits and Systems I: Regular Papers, no. 6, pp. 1872-1882, June 2014.

Jinho Han, Hyosup Won, Hyeon-Min Bae, “A 0.6-to-2.7-Gb/s Referenceless Parallel CDR with a Stochastic Dispersion-Tolerant Frequency Acquisition Technique”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no. 6, pp. 1219-1225, June 2014.

Kyeongha Kwon, Jonghyeok Yoon, Soon-Won Kwon, Jaehyeok Yang, Joon-Yeong Lee, Hyosup Won, Hyeon-Min Bae, “A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers”, IEEE International Solid-State Circuits Conference 2014, pp. 138–139, Feb. 2014.

Joon-Yeong Lee, Hyeon-Min Bae, “Application of Kalman Gain for Minimum Mean-Squared Phase-Error Bound in Bang-Bang CDRs”, IEEE Transactions on Circuits and Systems I: Regular Papers, no. 12, pp. 2825-2834, Dec. 2012.